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(parent: 312a6c0) | patch
imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask
authorYe Li <[email protected]>
Wed, 9 Mar 2016 08:13:48 +0000 (16:13 +0800)
committerStefano Babic <[email protected]>
Fri, 25 Mar 2016 12:55:54 +0000 (13:55 +0100)
commitb777789ebd193587a8e4700dce656523df821370
tree9afc5474db13a66b5d16e9a612db7a6f666038e9tree | snapshot
parent312a6c016a2d81aa3fbc605f5c0c315b6a4e3464commit | diff
imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask

Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.

Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Stefano Babic <[email protected]>
arch/arm/cpu/armv7/mx6/soc.c diff | blob | history
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